GREEN DDR3
First in the Market with Advanced DDR3
Double Data Rate Three, Synchronous DRAM, or DDR3 is the new generation of high performance, ultra-low-power memory interface technology used in high performance servers, desktops and notebooks. As the number one supplier in memory, Samsung continues to lead the industry with cutting-edge SDRAM products from the first DDR in 1997, DDR2 in 2001 and DDR3 in 2005. Samsung's high performance main memory solutions are based on JEDEC standards and leverage the company's leadership in advanced research and development of semiconductor process technology.
Samsung's DDR3 brings new levels of performance to notebooks, desktops and servers and pushes the envelope in key areas like power consumption, speed and bandwidth. Our recent 30nm class, 1.35V, 2Gb DDR3 is the world's first ultra-low-power memory technology, with more than a 76% power savings over traditional DDR2 at 2x the bandwidth. When you're ready to make a move to DDR3 or are considering upgrading your systems, we're here to provide the best optimal solution for enhancing your competitive edge.
Key Features
DDR3 supports data rates of 800 to 1600Mbps, with clock frequencies of 400 to 800 MHz and voltage ranges from 1.5V down to 1.35V. Samsung's advanced process technologies provide memory densities ranging from 1Gb to 4Gb, which help build a wide range of modules ranging from 1GB up to 32GB. In addition, our memory products are lead free and halogen free, attesting to our continuous support of a greener environment.
| Major Specification of DDR3 | |||
|---|---|---|---|
| Data Rate | 800-1866 Mbps | # of Banks | 1Gb/2Gb/4Gb/8Gb : 8Banks |
| System Assumption | 2 slots(loads) | Reset | Yes |
| Vdd/Vddq | 1.5V±0.075V, 1.35V(1.28V~1.45V) | ODT | Yes |
| Interface | 78 BGA for x4/x8, 96 BGA for x16 | Driver Calibration | Self calibration with ZQ pin |
| Source Sync | Bi-directional DQS (differential default) | Module Type | R-DIMM, VLP R-DIMM, U-DIMM, SoDIMM |
| Burst Length | BC4, BL8 (8bits prefetch) | Density | 1/2/4/8/16GB/32GB |
By Major Application
20nm 4Gb DDR3 is beneficial for all major EDP applications.
| Application | Features | 50nm 1Gb DDR3 | 40nm 1Gb DDR3 | 30nm 2Gb DDR3 | 20nm 4Gb DDR3 |
|---|---|---|---|---|---|
| Server | Power usage of 8GB module |
9.2W (1.5V) | 5.4W (1.35V) | 4.0W (1.35V) | 3.2W (1.35V) |
| Max Data Rate w/8GB | 800Mbps with 2DPC (16GB) |
800Mbps with 2DPC (16GB) |
1333Mbps with 1DPC (8GB) 1066Mbps with 2DPC (16GB) 800Mbps with 3DPC (24GB) |
1600Mbps with 1DPC (8GB) 1333Mbps with 2DPC (16GB) 800Mbps with 3DPC (24GB) |
|
| Max density per Channel |
16GB with 2DPC (Two 8GB modules) |
16GB with 2DPC (Two 8GB modules) |
32GB with 2DPC (Two 16GB modules) |
96GB with 3DPC (Three 32GB modules) |
|
| Notebook | Power usage of 4GB module |
2.47W (1.5V) | 1.82W (1.35V) | 1.23W (1.35V) | 0.97W (1.35V) |
| Max density per Channel |
4GB (2Rx8) | 4GB (2Rx8) | 8GB (2Rx8) | 16GB (2Rx8) | |
| Desktop | Max Speed | -1600Mbps | -1600Mbps | -1600Mbps | -1600Mbps |
| Max density per Cahnnel |
4GB with 2DPC (Two 2GB modules) |
4GB with 2DPC (Two 2GB modules) |
8GB with 2DPC (Two 4GB modules) |
16GB with 2DPC (Two 8GB modules) |
SEC internal data (Typical Value)
DPC DIMM per Channel
Samsung DDR2 vs. Samsung DDR3
| Features | DDR2 | DDR3 | Remark |
|---|---|---|---|
| Pin-out and Package | 60ball(x4/x8), 84ball(x16) FBGA | 78ball(x4/x8), 96ball(x16) FBGA | |
| Voltage | 1.8V | 1.5V/1.35V | Reduces memory system power demand |
| Density | 512Mb~2Gb | 1Gb~4Gb | Mono component |
| Internal banks | 4(512Mb), 8(1Gb/2Gb) | 8(1Gb/2Gb/4Gb) | |
| Prefetch | 4bit | 8bit | |
| tCK (DLL enabled) | 125MHz~400MHz | 300MHz~933MHz | Supports higher data rates |
| Burst length | BL4, BL8 | BC4, BL8 | BC4 provides relief from some BL8 requirements |
| Burst Type | Fixed | Fixed OTF (On-the-fly) | OTF allows switching between BC4 and BL8 |
| Speed per I/O | 400, 533, 667, 800 Mbps | 800, 1066, 1333, 1866 Mbps | Migration to higer speed |
| Additive latency | AL options(0, 1, 2, 3, 4) | AL options(0, CL-1, CL-2) | |
| Read latency | AL+CL CL=3, 4, 5, 6 | AL+CL CL=6, 7, 8, 9, 10 | |
| Write latency | RL-1 | AL+CWL CWL=5, 6, 7, 8 | |
| Data strobes | Sigle-ended Differential | Differential only | Reduce data strobe crosstalk |
| Data bus termination (Rtt) | ODT (On die termination) | ODT (On die termination) | |
| Rtt value | 50, 75, 150 Ohm | 20, 30, 40, 60, 120 Ohm | Supported for higher data rates |
| Rtt allowed | Read, Write, Standby | Write, Standby | |
| Dynamic ODT | None | 60, 120 Ohm | Support 2slots (Write only) |
| DQ driver impendance | 18 Ohm | 34 Ohm | Optimized for 2slots |
| Driver/ODT calibration | None | External register | Improves accuracy over voltage and temperature |
| Multi-purpose register | None | Four register |
Provides specialty readout |